1. Field of the Invention
The present invention relates generally to transistor logic circuits and, more particularly, to a low voltage, effectively differential, multiple input OR/NOR gate architecture.
2. Description of Related Art
Digital logic circuits, the basic building blocks of digital systems, are widely known and available. One of the most common and fundamental logic blocks is the "OR/NOR" gate. The output of the logical "OR" function is true if any input is true. The "NOR" function, so called because it is the logical "NOT OR," is the inverse of the OR function, and is only true when all inputs are false. In certain logic families, circuits which implement the OR function usually provide a NOR output as well. Thus, the circuits are commonly referred to as OR/NOR circuits.
It is often necessary to perform OR/NOR functions on more than two digital signals. One solution is to "cascade" two-input gates in order to create a circuit having the required number of inputs. Two-input gates can be designed to process differential signal inputs which greatly improves the circuit's noise margin characteristics. With differential inputs, any noise on one input is effectively cancelled due to the differential nature of the input signal. Noise margin is an important design criteria because the greater the noise margin the less chance a "noisy" signal will cause the gate to output the wrong value. However, cascading two-input gates increases the signal propagation delay, resulting in a slower overall circuit. Furthermore, the increase in the number of gates increases circuit costs in terms of power consumption and chip area.
Another prior art solution provides multiple inputs in a single circuit. In this circuit, a reference or bias voltage is applied to a reference transistor and the inputs are "single-ended" inputs and not differential. This multiple input circuit has a shorter propagation delay than cascading two-input gates, but has poor noise margin. Since the inputs are not really differential, noise may cause the output to switch incorrectly. For logic levels with a large voltage difference between the high and low logic levels, the noise margin may be sufficient. For circuits which use low voltage differences between the high and low logic levels, however, even the slightest noise can have a negative effect on circuit performance. For example, in the Emitter Coupled Logic (ECL) family, there is only a few tenths of a volt difference between the high and low logic levels. Any noise at the input exceeding half of the voltage difference can cause the output to switch to the incorrect value.
U.S. Pat. No. 5,408,145 discloses a CMOS NOR gate circuit having low power requirements and providing high speed switching between logic states. However, the circuit does not provide high noise immunity while requiring only single-ended inputs.
Thus, there is a need for a multiple input OR/NOR gate circuit which offers higher noise immunity to work with low voltage logic families. Also, it would be desirable to have a circuit which can be implemented in a very simple way, without a significant increase in the number of required transistors, and without an increase in power consumption.